1. Field of the Invention
The present invention is related to low offset, low noise auto-zeroed CMOS integrated circuit amplifiers and more in particular to read-out circuits for infrared detectors.
2. Description of the Related Art
A focal plane array comprises several individual detector elements (pixels). The number of pixels in a linear or focal plane array is increasing. The signal multiplexer is a high complexity detector specific integrated circuit, which reads all channels in parallel. The most commonly used detector circuits are the direct injection stage and the capacitive feedback transimpedance amplifier (CTIA).
A conventional detector buffer stage in a read-out circuit comprises a capacitive feedback transimpedance amplifier. The goal of the CTIA is to accumulate all detector current, preferably under the condition of zero bias or some reverse bias where the dynamic resistance is high. The amplifier keeps the detector at virtual ground while the detector current is flowing onto the capacitor, generating a voltage signal at the output proportional to the integration time and the signal current. The DC coupling between the detector and the CTIA yields an excellent linearity of the detector current to output voltage conversion. In the ideal condition of zero offset there is no influence of dark current and hence of dark current noise. In this case the detector shunt resistance does not play a role as there is no voltage difference over the detector. In practice however such a circuit has a major drawback, namely the op-amp input voltage non-uniformity (offset), causing fixed pattern noise on the read-out circuit and limiting the integration time. The circuit needs to be suited for measuring extremely small currents generated by infrared diodes with relatively low parallel resistance and needs therefore amplifiers with very small offset error voltages.
In order to correct said op-amp input voltage non-uniformity it is common to use an auto-zero (AZ) circuit. Such a scheme is for example discussed in “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilisation”, C. Enz and G. Themes, Proceedings of the IEEE, vol. 84, No. 11, November 1996, pp. 1584–1614) and in U.S. Pat. No. 4,884,039. This patent discloses a differential amplifier including a linear offset operation circuit comprising sources providing a reference voltage and an offset correction voltage and a pair of auxiliary transistors for supplying currents for correcting offset errors of the amplifier.
Some numerical results on residual offset voltages can be found in ‘A micropower CMOS instrumentation amplifier’, IEEE J.Solid-State Circ., vol.SC-20, pp.805–807, June 1985.